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FEATURES 12-Bit Multiplying DACs Guaranteed Specifications with +3.3 V/+5 V Supply 0.5 LSBs INL and DNL Low Power: 5 W typ Fast Interface 40 ns Strobe Pulsewidth (AD7943) 40 ns Write Pulsewidth (AD7945, AD7948) Low Glitch: 60 nV-s with Amplifier Connected Fast Settling: 600 ns to 0.01% with AD843 APPLICATIONS Battery-Powered Instrumentation Laptop Computers Upgrades for All 754x Series DACs (5 V Designs)
VREF CLR LD1 LD2 SRI
+3.3 V/+5 V Multiplying 12-Bit DACs AD7943/AD7945/AD7948
FUNCTIONAL BLOCK DIAGRAMS
VDD RFB IOUT1 IOUT2 AGND
AD7943
12-BIT DAC
DAC REGISTER
INPUT SHIFT REGISTER
SRO
STB1 STB2 STB3 STB4 VDD RFB
DGND
GENERAL DESCRIPTION
The AD7943, AD7945 and AD7948 are fast 12-bit multiplying DACs that operate from a single +5 V supply (Normal Mode) and a single +3.3 V to +5 V supply (Biased Mode). The AD7943 has a serial interface, the AD7945 has a 12-bit parallel interface, and the AD7948 has an 8-bit byte interface. They will replace the industry-standard AD7543, AD7545 and AD7548 in many applications, and they offer superior speed and power consumption performance. The AD7943 is available in 16-lead DIP, 16-lead SOP (Small Outline Package) and 20-lead SSOP (Shrink Small Outline Package). The AD7945 is available in 20-lead DIP, 20-lead SOP and 20lead SSOP. The AD7948 is available in 20-lead DIP, 20-lead SOP and 20lead SSOP.
AD7945
VREF 12-BIT DAC 12 CS WR INPUT LATCH 12 DB11-DB0 VDD RFB DGND
IOUT1 AGND
VREF
12-BIT DAC 12 DATA OVERRIDE LOGIC 12 DAC REGISTER 12 INPUT REGISTERS 12 DATA STEERING LOGIC 8 DB7-DB0 DGND CONTROL LOGIC
IOUT1 AGND
AD7948
DF/DOR CTRL
LDAC WR CSLSB CSMSB
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD7943/AD7945/AD7948-SPECIFICATIONS1
NORMAL MODE
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error TMIN to TMAX Gain Temperature Coefficient 4 Output Leakage Current IOUT1 @ +25C TMIN to TMAX REFERENCE INPUT Input Resistance DIGITAL INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH , Input Current CIN, Input Capacitance4 DIGITAL OUTPUT (AD7943 SRO) Output Low Voltage (V OL) Output High Voltage (V OH) POWER REQUIREMENTS VDD Range Power Supply Sensitivity4 Gain/VDD IDD (AD7943)
(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V; VREF = +10 V; TA = TMIN to TMAX, unless otherwise noted. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 = AGND = 0 V; VREF = +10 V; T A = TMIN to TMAX, unless otherwise noted.)
B Grades2 T Grade2, 3 12 0.5 0.5 2 2 5 12 0.5 0.5 2 2 5 Units Bits LSB max LSB max Test Conditions/Comments 1 LSB = VREF/212 = 2.44 mV when VREF = 10 V All Grades Guaranteed Monotonic over Temperature
LSB max ppm FSR/C typ ppm FSR/C max
10 100 6 12 2.4 0.8 1 10 0.2 VDD - 0.2 4.5/5.5 -75 5
10 100 6 12 2.4 0.8 1 10 0.2 VDD - 0.2 4.5/5.5 -75 5
nA max nA max k min k max V min V max A max pF max
See Terminology Section Typically 20 nA over Temperature Typical Input Resistance = 9 k
For 1 CMOS Load V max V min V min/V max dB typ A max
IDD (AD7945, AD7948)
5
5
A max
VINH = VDD - 0.1 V min, V INL = 0.1 V max. SRO Open Circuit. No STB Signal. Typically 1 A. Typically 100 A with a 1 MHz STB Frequency. At Input Levels of 0.8 V and 2.4 V, IDD Is Typically 2.5 mA. VINH = VDD - 0.1 V min, V INL = 0.1 V max. Typically 1 A. At Input Levels of 0.8 V and 2.4 V, IDD Is Typically 2.5 mA.
NOTES 1 The AD7943, AD7945 and AD7948 are specified in the normal current mode configuration and in the biased current mode for single-supply applications. Figures 14 and 15 are examples of normal mode operation. 2 Temperature ranges as follows: B Grades: -40C to +85C; T Grade: -55C to +125C. 3 The T Grade applies to the AD7945 only. 4 Guaranteed by design. Specifications subject to change without notice.
-2-
REV. B
AD7943/AD7945/AD7948
SPECIFICATIONS1
BIASED MODE
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error @ +25C TMIN to TMAX Gain Temperature Coefficient3 Output Leakage Current IOUT1 @ +25C TMIN to TMAX Input Resistance @ IOUT2 Pin (AD7943) @ AGND Pin (AD7945, AD7948) DIGITAL INPUTS VINH, Input High Voltage @ VDD = +5 V VINH, Input High Voltage @ VDD = +3.3 V VINL, Input Low Voltage @ VDD = +5 V VINL, Input Low Voltage @ VDD = +3.3 V IINH, Input Current CIN, Input Capacitance3 DIGITAL OUTPUT (SRO) Output Low Voltage (VOL) Output High Voltage (VOH) POWER REQUIREMENTS VDD Range Power Supply Sensitivity3 Gain/VDD IDD (AD7943)
(AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND = 1.23 V; VREF = +0 V to 2.45 V; TA = TMIN to TMAX, unless otherwise noted.)
A Grades2 Units 12 1 0.9 3 4 2 5 Bits LSB max LSB max LSB max LSB max ppm FSR/C typ ppm FSR/C max See Terminology Section 10 100 6 6 2.4 2.1 0.8 0.6 1 10 0.2 VDD - 0.2 3.0/5.5 -75 5 nA max nA max k min k min V min V min V max V max A max pF max For 1 CMOS Load V max V min V min/V max dB typ A max Test Conditions/Comments 1 LSB = (VIOUT1 - VREF)/212 = 300 V When VIOUT1 = 1.23 V and VREF = 0 V All Grades Guaranteed Monotonic over Temperature
Typically 20 nA over Temperature This Varies with DAC Input Code
IDD (AD7945, AD7948)
5
A max
VINH = VDD - 0.1 V min, VINL = 0.1 V max. SRO Open Circuit; No STB Signal; Typically 1 A. Typically 100 A with 1 MHz STB Frequency. VINH = VDD - 0.1 V min, VINL = 0.1 V max. Typically 1 A.
NOTES 1 These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a "-B" suffix (for example: AD7943AN-B). Figure 16 is an example of Biased Mode Operation. 2 Temperature ranges as follows: A Versions: -40C to +85C. 3 Guaranteed by design. Specifications subject to change without notice.
REV. B
-3-
AD7943/AD7945/AD7948
NORMAL MODE
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time
AC PERFORMANCE CHARACTERISTICS
B Grades 600 T Grade 700 Units ns typ Test Conditions/Comments To 0.01% of Full-Scale Range. VREF = +10 V; DAC Latch Alternately Loaded with All 0s and All 1s Measured with VREF = 0 V. DAC Latch Alternately Loaded with All 0s and All 1s DAC Latch Loaded with All 0s All 1s Loaded to DAC All 0s Loaded to DAC Feedthrough to the DAC Output with LD1, LD2 High and Alternate Loading of All 0s and All 1s into the Input Shift Register Feedthrough to the DAC Output with CS High and Alternate Loading of All 0s and All 1s to the DAC Bus
(AD7943: VDD = +4.5 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 0 V. AD7945, AD7948: VDD = +4.5 V to +5.5 V; VIOUT1 =AGND = 0 V. VREF = 6 V rms, 1 kHz sine wave; TA = TMIN to TMAX; DAC output op amp is AD843; unless otherwise noted.) These characteristics are included for Design Guidance and are not subject to test.
Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough (AD7943)
60 -75 60 30 5
60 -75 60 30 5
nV-s typ dB max pF max pF max nV-s typ
Digital Feedthrough (AD7945, AD7948) 5
5
nV-s typ
Total Harmonic Distortion Output Noise Spectral Density @ 1 kHz
Specifications subject to change without notice.
-83 35
-83 35
dB typ nV/Hz typ All 1s Loaded to DAC. VREF = 0 V. Output Op Amp Is OP07
AC PERFORMANCE CHARACTERISTICS
BIASED MODE (AD7943: VDD = +3 V to +5.5 V; VIOUT1 = VIOUT2 = AGND = 1.23 V. AD7945, AD7948: VDD = +3 V to +5.5 V; VIOUT1 = AGND = 1.23 V. VREF = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; TA = TMIN to TMAX ; unless otherwise noted.) These characteristics are included for Design Guidance and are not subject to test.
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough A Grades 5 60 -75 60 30 5 Units s typ nV-s typ dB max pF max pF max nV-s typ Test Conditions/Comments To 0.01% of Full-Scale Range. VREF = 0 V DAC Latch Alternately Loaded with All 0s and All 1s VREF = 1.23 V. DAC Register Alternately Loaded with All 0s and All 1s DAC Latch Loaded with All 0s All 1s Loaded to DAC All 0s Loaded to DAC Feedthrough to the DAC Output with LD1, LD2 High and Alternate Loading of All 0s and All 1s into the Input Shift Register Feedthrough to the DAC Output with CS High and Alternate Loading of All 0s and All 1s to the DAC Bus
Digital Feedthrough (AD7945, AD7948)
5
nV-s typ
Total Harmonic Distortion Output Noise Spectral Density @ 1 kHz
Specifications subject to change without notice.
-83 25
dB typ nV/Hz typ All 1s Loaded to DAC. VREF = 1.23 V
-4-
REV. B
AD7943/AD7945/AD7948 AD7943 TIMING SPECIFICATIONS1 (T
Parameter tSTB tDS tDH tSRI tLD tCLR tASB tSV3
2
A
= TMIN to TMAX, unless otherwise noted)
Units ns min ns min ns min ns min ns min ns min ns min ns max Description STB Pulsewidth Data Setup Time Data Hold Time SRI Data Pulsewidth Load Pulsewidth CLR Pulsewidth Min Time Between Strobing Input Shift Register and Loading DAC Register STB Clocking Edge to SRO Data Valid Delay
Limit @ VDD = +3 V to +3.6 V 60 15 35 55 55 55 0 60
Limit @ VDD = +4.5 V to +5.5 V 40 10 25 35 35 35 0 35
NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 s on any digital input. 2 STB mark/space ratio range is 60/40 to 40/60. 3 tSV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. Specifications subject to change without notice.
t STB
STB1, STB2, STB4
STB3
tDH t DS t SRI
SRI DB11(N) (MSB) DB10(N) DB0(N)
t ASB
LD1, LD2, CLR SRO
t LD, t CLR
t SV
DB10(N-1) DB0(N-1)
Figure 1. AD7943 Timing Diagram
1.6mA
IOL
TO OUTPUT PIN
+2.1V CL 50pF 200 A IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
REV. B
-5-
AD7943/AD7945/AD7948 AD7945 TIMING SPECIFICATIONS1 (T = T
A MIN to T MAX,
unless otherwise noted)
Units ns min ns min ns min ns min ns min Description Data Setup Time Data Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulsewidth
Parameter tDS tDH tCS tCH tWR
Limit @ VDD = +3 V to +3.6 V 35 10 60 0 60
Limit @ VDD = +4.5 V to +5.5 V 20 10 40 0 40
NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice.
tCS
CS
tCH
tWR
WR
tDS
DB11-DB0
tDH
DATA VALID
Figure 3. AD7945 Timing Diagram
AD7948 TIMING SPECIFICATIONS1 (T = T
A
MIN
to TMAX, unless otherwise noted)
Units ns min ns min ns min ns min ns min ns min ns min Description Data Setup Time Data Hold Time CSMSB or CSLSB to WR Setup Time CSMSB or CSLSB to WR Hold Time LDAC to WR Setup Time LDAC to WR Hold Time Write Pulsewidth
Parameter tDS tDH tCWS tCWH tLWS tLWH tWR
Limit @ VDD = +3 V to +3.6 V 45 10 0 0 0 0 60
Limit @ VDD = +4.5 V to +5.5 V 30 10 0 0 0 0 40
NOTES 1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice.
tCWS
CSMSB
tCWH tCWS tCWH
CSLSB
tLWS
LDAC
tLWH
tWR
WR
tWR tDH tDH
DATA VALID
tDS
DB7-DB0
DATA VALID
tDS
Figure 4. AD7948 Timing Diagram
-6-
REV. B
AD7943/AD7945/AD7948
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +6 V IOUT1 to DGND . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V IOUT2 to DGND . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . -0.3 V to VDD + 0.3 V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C DIP Package, Power Dissipation . . . . . . . . . . . . . . . . 670 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 116C/W Lead Temperature, Soldering, (10 sec) . . . . . . . . . . +260C
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 132C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7943/AD7945/AD7948 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD7943BN AD7943BR AD7943BRS AD7943AN-B AD7943ARS-B AD7945BN AD7945BR AD7945BRS AD7945AN-B AD7945ARS-B AD7945TQ AD7948BN AD7948BR AD7948BRS AD7948AN-B AD7948ARS-B
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Linearity Error (LSBs) 0.5 0.5 0.5 1 1 0.5 0.5 0.5 1 1 1 0.5 0.5 0.5 1 1
Nominal Supply Voltage +5 V +5 V +5 V +3.3 V to +5 V +3.3 V to +5 V +5 V +5 V +5 V +3.3 V to +5 V +3.3 V to +5 V +5 V +5 V +5 V +5 V +3.3 V to +5 V +3.3 V to +5 V
Package Option1 N-16 R-16 RS-20 N-16 RS-20 N-20 R-20 RS-20 N-20 RS-20 Q-20 N-20 R-20 RS-20 N-20 RS-20
NOTE 1 N = Plastic DIP; R = SOP (Small Outline Package); RS = SSOP (Shrink Small Outline Package); Q = Cerdip.
REV. B
-7-
AD7943/AD7945/AD7948
TERMINOLOGY Relative Accuracy Output Capacitance
This is the capacitance from the IOUT1 pin to AGND.
Output Voltage Settling Time
Relative Accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error and is normally expressed in Least Significant Bits or as a percentage of fullscale reading.
Differential Nonlinearity
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified both with the AD843 as the output op amp in the normal current mode and with the AD820 in the biased current mode.
Digital to Analog Glitch Impulse
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Gain Error
Gain Error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error has been adjusted out and is expressed in Least Significant Bits. Gain error is adjustable to zero with an external potentiometer.
Output Leakage Current
This is the amount of charge injected into the analog output when the inputs change state. It is specified as the area of the glitch in nV-s. It is measured with the reference input connected to AGND and the digital inputs toggled between all 1s and all 0s. As with Settling Time, it is specified with both the AD817 and the AD820.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded in the DAC.
Digital Feedthrough
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s.
When the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the IOUT1 pin and subsequently on the op amp output. This noise is digital feedthrough.
PIN CONFIGURATIONS
DIP/SOP
SSOP
DIP/SOP/SSOP
DIP/SOP/SSOP
IOUT1 1 IOUT2
2
16 15
RFB VREF VDD
IOUT1 1 IOUT2 2 AGND 3 STB1 4
20 19
RFB VREF VDD
IOUT1 1 AGND 2 DGND 3 DB11 4
20 19
RFB VREF VDD
IOUT1 1 AGND 2 DGND 3 CSMSB 4
20 19
RFB VREF VDD
AGND 3 STB1 4
AD7943
14
AD7943
18
AD7945
18
AD7948
18
TOP VIEW 13 CLR (Not to Scale) 12 DGND LD1 5
11 10 9
TOP VIEW 17 CLR (Not to Scale) 16 NC NC 5 NC 6
15 14 13 12 11
TOP VIEW 17 WR (Not to Scale) 16 CS DB10 5 DB9 6 DB8 7 DB7 8 DB6 9 DB5 10
15 14 13 12 11
TOP VIEW 17 WR (Not to Scale) 16 CSLSB 5 DF/DOR CTRL 6 DB7 (MSB) 7 DB6 8 DB5 9 DB4 10
15 14 13 12 11
SRO 6 SRI
7
STB4 STB3 LD2
NC DGND STB4 STB3 LD2
DB0 DB1 DB2 DB3 DB4
LDAC DB0 (LSB) DB1 DB2 DB3
LD1 7 SRO 8 SRI 9 STB2 10
STB2 8
NC = NO CONNECT
-8-
REV. B
AD7943/AD7945/AD7948
AD7943 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic IOUT1 IOUT2 AGND
Description DAC current output terminal 1. DAC current output terminal 2. This should be connected to the AGND pin. This pin connects to the back gates of the current steering switches. In normal operation, it should be connected to the signal ground of the system. In biased single-supply operation it may be biased to some voltage between 0 V and the 1.23 V. See Figure 11 for more details. This is the Strobe 1 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB2, STB4 must be low. Active low inputs. When both of these are low, the DAC register is updated and the output will change to reflect this. Serial Data Input. Data on this line will be clocked into the input shift register on one of the Strobe inputs, when they are enabled. This is the Strobe 2 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB1, STB4 must be low. This is the Strobe 3 input. Data is clocked into the input shift register on the falling edge of this signal. STB1, STB2, STB4, must be low. This is the Strobe 4 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB1, STB2 must be low. Digital Ground. Asynchronous CLR input. When this input is taken low, all 0s are loaded to the DAC latch. Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode Operation. DAC reference input. DAC feedback resistor pin.
AD7945 PIN FUNCTION DESCRIPTIONS
STB1 LD1, LD2 SRI STB2 STB3 STB4 DGND CLR VDD VREF RFB
Pin Mnemonic IOUT1 AGND DGND DB11-DB0 CS WR VDD VREF RFB
Description DAC current output terminal 1. This pin connects to the back gates of the current steering switches. The DAC IOUT2 terminal is also connected internally to this point. Digital Ground. Digital Data Inputs. Active Low, Chip Select Input. Active Low, Write Input. Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode Operation. DAC reference input. DAC feedback resistor pin.
REV. B
-9-
AD7943/AD7945/AD7948
AD7948 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic IOUT1 AGND DGND CSMSB DF/DOR
Description DAC current output terminal 1. Normally terminated at the virtual ground of output amplifier. Analog Ground Pin. This pin connects to the back gates of the current steering switches. The DAC IOUT2 terminal is also connected internally to this point. Digital Ground Pin. Chip Select Most Significant Byte. Active Low Input. Used in combination with WR to load external data into the input register or in combination with LDAC and WR to load external data into both input and DAC registers. Data Format/Data Override. When this input is low, data in the DAC register is forced to one of two override codes selected by CTRL. When the override signal is removed, the DAC output returns to reflect the value in the DAC register. With DF/DOR high, CTRL selects either a left or right justified input data format. For normal operation, DF/DOR is held high. See Table I.
Table I. Truth Table for DF/DOR CTRL
DF/DOR 0 0 1 1 CTRL DB7-DB0 LDAC CSLSB
CTRL 0 1 0 1
Function DAC Register Contents Overridden by All 0s DAC Register Contents Overridden by All 1s Left-Justified Input Data Selected Right-Justified Input Data Selected
Control Input. See DF/DOR description. Digital Data Inputs. Load DAC input, active low. This signal, in combination with others, is used to load the DAC register from either the input register or the external data bus. Chip Select Least Significant (LS) Byte. Active Low Input. Used in combination with WR to load external data into the input register or in combination with WR and LDAC to load external data into both input and DAC registers.
Table II. Truth Table for AD7948 Write Operation
WR 0 0 0 0 0 1 WR VDD VREF RFB
CSMSB 1 1 0 0 1 X
CSLSB 0 0 1 1 1 X
LDAC 1 0 1 0 0 X
Function Load LS Byte to Input Register Load LS Byte to Input Register and DAC Register Load MS Byte to Input Register Load MS Byte to Input Register and DAC Register Load Input Register to DAC Register No Data Transfer
Write input, active low. This active low signal, in combination with others is used in loading external data into the AD7948 input register and in transferring data from the input register to the DAC register. Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode Operation. DAC reference input. DAC feedback resistor pin.
-10-
REV. B
AD7943/AD7945/AD7948 Typical Performance Curves
0.5 VDD = +5V TA = +25 C OP AMP = AD843 LINEARITY ERROR - LSBS 0.25 0.50 VDD = +5V VREF = +10V OP AMP = AD843 TA = +25 C 0.4
DNL - LSBS
0.3
0.00
0.2
-0.25
0.1
0
-0.50 2 4 6 VREF - Volts 8 10 0 1024 2048 INPUT CODE 3072 4095
Figure 5. Differential Nonlinearity Error vs. VREF (Normal Mode)
1.0 0.9 0.8 0.7
INL - LSBS
Figure 7. All Codes Linearity In Normal Mode (V DD = +5 V)
VDD = +5V TA = +25 C OP AMP = AD843
6 VDD = +3.3V TA = +25 C OP AMP = AD820
5
0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 6 VREF - Volts 8 10
INL, DNL - LSBS
4
3
2
1
0 0.2
0.4
0.6 0.8 1.0 |VREF - VBIAS| - Volts
1.2
1.4
Figure 6. Integral Nonlinearity Error vs. VREF (Normal Mode)
Figure 8. Linearity Error vs. VREF (Biased Mode)
REV. B
-11-
AD7943/AD7945/AD7948
1.00 VDD = +3.3V VREF = 0V VBIAS = 1.23V OP AMP = AD820 TA = +25 C
LINEARITY ERROR - LSBS
0.50
5V
100 90
200ns
0.00
VDD = +5V TA = +25 C VREF = 0V OP AMP = AD711 AD711 OUTPUT
10 0%
-0.50
50mV
-1.00 0 1024 2048 INPUT CODE 3072 4095
200ns
Figure 9. All Codes Linearity in Biased Mode (VDD = +3.3 V)
-50 -55 -60 -65 THD - dBs -70 -75 -80 -85 -90 -95 -100 100 1k 10k FREQUERCY - Hz 100k VDD = +5V TA = +25 C VIN = 6V rms OP AMP = AD711
Figure 11. Digital-to-Analog Glitch Impulse
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1k 10k 100k FREQUENCY - Hz 1M 10M DAC LOADED WITH ALL 0S VDD = +5V TA = +25 C VIN = 20V p-p OP AMP = AD711
DAC LOADED WITH ALL 1S
Figure 10. Total Harmonic Distortion vs. Frequency
Figure 12. Multiplying Frequency Response vs. Digital Code
-12-
REV. B
AD7943/AD7945/AD7948
GENERAL DESCRIPTION D/A Section UNIPOLAR BINARY OPERATION (Two-Quadrant Multiplication)
The AD7943, AD7945 and AD7948 are 12-bit current-output D/A converters. A simplified circuit diagram is shown in Figure 13. The DAC architecture is segmented. This means that the 2 MSBs of the 12-bit data word are decoded to drive the three switches A, B and C. The remaining 10 bits of the data word drive the switches S0 to S9 in a standard inverting R-2R ladder configuration. Each of the switches A to C steers 1/4 of the total reference current into either IOUT1 or IOUT2 with the remaining 1/4 of the total current passing through the R-2R section. Switches S9 to S0 steer binarily weighted currents into either IOUT1 or IOUT2. If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Thus, the input resistance seen at VREF is always constant. It is equal to R/2. The VREF input may be driven by any reference voltage or current, ac or dc that is within the Absolute Maximum Ratings. The device provides access to the VREF, RFB, and IOUT1 terminals of the DAC. This makes the device extremely versatile and allows it to be configured in several different operating modes. Examples of these are shown in the following sections. The AD7943 also has a separate IOUT2 pin. In the AD7945 and AD7948 this is internally tied to AGND. When an output amplifier is connected in the standard configuration of Figure 14, the output voltage is given by: VOUT = -D x VREF where D is the fractional representation of the digital word loaded to the DAC. D can be set from 0 to 4095/4096, since it has 12-bit resolution.
VREF R R R
Figure 14 shows the standard unipolar binary connection diagram for the AD7943, AD7945 and AD7948. When VIN is an ac signal, the circuit performs two-quadrant multiplication. Resistors R1 and R2 allow the user to adjust the DAC gain error. With a specified gain error of 2 LSBs over temperature, these are not necessary in many applications. Circuit offset is due completely to the output amplifier offset. It can be removed by adjusting the amplifier offset voltage. Alternatively, choosing a low offset amplifier makes this unnecessary. A1 should be chosen to suit the application. For example, the OP07 is ideal for very low bandwidth applications (10 kHz or
R2 10 RFB VREF VIN R1 20 DAC IOUT1 IOUT2 A1 VOUT A1: OP07 AD711 AD843 AD845 C1
AD7943/45/48
AGND NOTES
SIGNAL GROUND
1. ONLY ONE DAC IS SHOWN FOR CLAIRITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5 - 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
Figure 14. Unipolar Binary Operation
lower) while the AD711 is suitable for medium bandwidth applications (200 kHz or lower). For high bandwidth applications of greater than 200 kHz, the AD843 and AD847 offer very fast settling times. The code table for Figure 14 is shown in Table III.
Table III. Unipolar Binary Code
2R C B
2R A
2R S9
2R S8
2R S0
2R
2R
Digital Input MSB LSB
RFB IOUT1 IOUT2
Analog Output (VOUT as Shown in Figure 14) -VREF (4095/4096) -VREF (2049/4096) -VREF (2048/4096) -VREF (2047/4096) -VREF (1/4096) -VREF (0/4096) = 0
R/2
SHOWN FOR ALL 1S ON DAC
Figure 13. Simplified D/A Circuit Diagram
1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
NOTE Nominal LSB size for the circuit of Figure 14 is given by: V REF (1/4096).
REV. B
-13-
AD7943/AD7945/AD7948
BIPOLAR OPERATION (Four-Quadrant Multiplication) SINGLE SUPPLY APPLICATIONS
Figure 15 shows the standard connection diagram for bipolar operation of the AD7943, AD7945 and AD7948. The coding is offset binary as shown in Table IV. When VIN is an ac signal, the circuit performs four-quadrant multiplication. Resistors R1 and R2 are for gain error adjustment and are not needed in many applications where the device gain error specifications are adequate. To maintain the gain error specifications, resistors R3, R4 and R5 should be ratio matched to 0.01%.
R4 20k R2 10 RFB VIN VREF DAC R1 20 IOUT1 IOUT2 A1 10k A2 VOUT C1 R3 R5 20k
The "-B" versions of the devices are specified and tested for single supply applications. Figure 16 shows the recommended circuit for operation with a single +5 V to +3.3 V supply. The IOUT2 and AGND terminals are biased to 1.23 V. Thus, with 0 V applied to the VREF terminal, the output will go from 1.23 V (all 0s loaded to the DAC) to 2.46 V (all 1s loaded). With 2.45 V applied to the VREF terminal, the output will go from 1.23 V (all 0s loaded) to 0.01 V (all 1s loaded). It is important when considering INL in a single-supply system to realize that most single-supply amplifiers cannot sink current and maintain zero volts at the output. In Figure 16, with VREF = 2.45 V the required sink current is 200 A. The minimum output voltage level is 10 mV. Op amps like the OP295 are capable of maintaining this level while sinking 200 A. Figure 16 shows the IOUT2 and AGND terminals being driven by an amplifier. This is to maintain the bias voltage at 1.23 V as the impedance seen looking into the IOUT2 terminal changes. This impedance is code dependent and varies from infinity (all 0s loaded in the DAC) to about 6 k minimum. The AD589 has a typical output resistance of 0.6 and it can be used to drive the terminals directly. However, this will cause a typical linearity degradation of 0.2 LSBs. If this is unacceptable then the buffer amplifier is necessary. Figure 9 shows the typical linearity performance of the AD7943/AD7945/AD7948 when used as in Figure 16 with VDD set at +3.3 V and VREF = 0 V.
+3.3V
AD7943/45/48
AGND SIGNAL GROUND NOTES 1. ONLY ONE DAC IS SHOWN FOR CLAIRITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5 - 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 15. Bipolar Operation (Four-Quadrant Multiplication)
Suitable dual amplifiers for use with Figure 15 are the OP270 (low noise, low bandwidth, 15 kHz), the AD712 (medium bandwidth, 200 kHz) or the AD827 (wide bandwidth, 1 MHz).
Table IV. Bipolar (Offset Binary) Code
VDD VREF
RFB IOUT1 DAC IOUT2
C1 A1 VOUT A1: OP295 AD822 OP283
Table Digital Input MSB LSB 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Analog Output (VOUT as Shown in Figure 15) +VREF (2047/2048) +VREF (1/2048) +VREF (0/2048) = 0 -VREF (1/2048) -VREF (2047/2048) -VREF (2048/2048) = -VREF
VIN
AD7943/45/48
AGND DGND +5V 5.6k AD589 SIGNAL GROUND A1
Figure 16. Single Supply System
NOTE Nominal LSB size for the circuit of Figure 15 is given by: V REF (1/2048).
-14-
REV. B
AD7943/AD7945/AD7948
MICROPROCESSOR INTERFACING AD7943 to ADSP-2101 Interface AD7945 to MC68000 Interface
Figure 17 shows the AD7943 to ADSP-2101 interface diagram. The DSP is set up for alternate inverted framing with an internally generated SCLK. TFS from the ADSP-2101 drives the STB1 input on the AD7943. The serial word length should be set at 12. This is done by making SLEN = 11 (1011 binary). The SLEN field is Bits 3-0 in the SPORT control register (0x3FF6 for SPORT0 and 0x3FF2 for SPORT1). With the 16 MHz version of the ADSP-2101, the maximum output SCLK is 8 MHz. The AD7943 setup and hold time of 10 ns and 25 ns mean that it is compatible with the DSP when running at this speed. The OUTPUT FLAG drives both LD1 and LD2 and is brought low to update the DAC register and change the analog output.
+5V
Figure 19 shows the MC68000 interface to the AD7945. The appropriate data is written into the DAC in one MOVE instruction to the appropriate memory location.
A1 - A23
MC68000
AS DTACK WR R/W ADDRESS DECODE CS
AD7945
D15 - D0
DB11 - DB0
ADSP-2101
CLR TFS SCLK DT OUTPUT FLAG STB1 STB3 SRI LD1 LD2
AD7943
Figure 19. AD7945 to MC68000 Interface
AD7948 to Z80 Interface
Figure 20 is the interface between the AD7948 and the 8-bit bus of the Z80 processor. Three write operations are needed to load the DAC. The first two load the MS byte and the LS byte and the third brings the LDAC low to update the output.
STB4
STB2
A0 - A15
ADDRESS BUS
Figure 17. AD7943 to ADSP-2101 Interface
AD7943 to DSP56001 Interface
Z80
MREQ ADDRESS DECODE
CSMSB CSLSB LDAC
Figure 18 shows the interface diagram for the AD7943 to the DSP56001. The DSP56001 is configured for normal mode synchronous operation with gated clock. The serial clock, SCK, is set up as an output from the DSP and the serial word length is set for 12 bits (WL0 = 1, WL1 = 0, in Control Register A). SCK from the DSP56001 is applied to the AD7943 STB3 input. Data from the DSP56000 is valid on the falling edge of SCK and this is the edge which clocks the data into the AD7943 shift register. STB1, STB2 and STB4 are tied low on the AD7943 to permanently enable the STB3 input. When the 12-bit serial word has been written to the AD7943, the LD1, LD2 inputs are brought low to update the DAC register.
+5V
AD7948
WR WR
D7 - D0
DB7 - DB0
DATA BUS
Figure 20. AD7948 to Z80 Interface
DSP56001
CLR
AD7943
SCK STD OUTPUT FLAG
STB3 SRI LD1 LD2 STB1 STB2 STB4
Figure 18. AD7943 to DSP56001 Interface
REV. B
-15-
AD7943/AD7945/AD7948
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP (N-16)
16-Lead SOP (R-16)
0.4133 (10.50) 0.3977 (10.00)
16 9
16 1
9 8
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.325 (8.26) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
1
8
PIN 1 0.015 (0.381) 0.008 (0.204) 0.0118 (0.30) 0.0040 (0.10)
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) x 45 0.0098 (0.25)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.0500 (1.27) BSC
8 0.0500 (1.27) 0.0192 (0.49) SEATING 0.0125 (0.32) 0 0.0157 (0.40) 0.0138 (0.35) PLANE 0.0091 (0.23)
20-Lead Plastic DIP (N-20)
20-Lead Cerdip (Q-20)
1.060 (26.90) 0.925 (23.50)
20 1
0.005 (0.13) MIN
20
0.098 (2.49) MAX
11
0.280 (7.11) 10 0.240 (6.10) PIN 1 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
11
0.310 (7.87) 0.220 (5.59) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.200 (5.08) MAX 0.015 (0.381) 0.008 (0.204) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC
1 10
PIN 1 1.060 (26.92) MAX
0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.320 (8.13) 0.290 (7.37)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.070 (1.78) SEATING 15 0.030 (0.76) PLANE 0
0.015 (0.38) 0.008 (0.20)
20-Lead SOP (R-20)
0.5118 (13.00) 0.4961 (12.60)
20 11
20-Lead SSOP (RS-20)
0.295 (7.50) 0.271 (6.90)
0.4193 (10.65) 0.3937 (10.00)
20
11
0.2992 (7.60) 0.2914 (7.40)
1
10
0.311 (7.9) 0.301 (7.64)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) x 45 0.0098 (0.25)
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.78) 0.066 (1.67)
0.0118 (0.30) 0.0040 (0.10)
8 0.0500 (1.27) 0.0500 0.0192 (0.49) 0 0.0157 (0.40) (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23)
0.008 (0.203) 0.002 (0.050)
0.0256 (0.65) BSC
8 SEATING 0.009 (0.229) 0 PLANE 0.005 (0.127)
0.037 (0.94) 0.022 (0.559)
-16-
REV. B
PRINTED IN U.S.A.
1
10
0.212 (5.38) 0.205 (5.21)
C1901b-0-5/98
0.840 (21.34) 0.745 (18.92)
0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00)

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